There are numerous constraints on the design of augmented actuality programs. Not the least of which is that “it’s important to look presentable while you’re strolling round,” Meta analysis scientist Tony Wu instructed engineers Tuesday on the IEEE International Solid State Circuits Conference (ISSCC). “You possibly can’t have a shoebox in your face on a regular basis.”
An AR system additionally should be light-weight and may’t throw off plenty of warmth. And it must be miserly with energy as a result of no one desires to must recharge wearable electronics each couple of hours. Then once more, if you happen to’ve received a flaming scorching shoebox in your face, you may be thankful for a brief battery life.
The 3D chip may monitor two palms concurrently utilizing 40 % much less power than a single-die may do with just one hand. What’s extra, it did so 40 % sooner.
Wu is a part of the Meta staff engaged on the silicon smarts to make an AR system, called Aria, that’s the as little like a scorching shoebox as they’ll make it. A giant a part of the answer, Wu instructed engineers, is 3D chip integration technology. At ISSCC, Meta detailed how the corporate’s prototype AR processor makes use of 3D to do extra in the identical space and with the identical quantity or much less power.
Meta’s prototype chip has each logic and reminiscence on every silicon die. They’re bonded face-to-face and through-silicon vias (TSVs) carry information and energy to each.Meta
The prototype chip is 2 ICs of equal measurement—4.1 x 3.7 millimeters. They’re bonded collectively in a course of referred to as face-to-face wafer-to-wafer hybrid bonding. Because the title implies, it includes flipping two absolutely processed wafers in order that they’re going through one another and bonding them, so their interconnects hyperlink collectively straight. (The “hybrid bonding” half means it’s a direct copper-to-copper connection. No solder wanted.)
The TSMC technology used for this meant the 2 items of silicon may type a vertical connection roughly each 2 micrometers. The prototype didn’t absolutely make use of this density: It required round 33,000 sign connections between the 2 items of silicon and 6 million energy connections. The underside die makes use of through-silicon vias—vertical connections bored down by the silicon—to get alerts out of the chip and energy in.
3D stacking meant the staff may improve the chip’s computing energy—letting it deal with greater duties—with out including to its measurement. The chip’s machine studying unit has 4 compute cores on the underside die and 1 megabyte of native reminiscence, however the prime die provides one other 3 MB, accessible by 27,000 vertical information channels on the identical velocity and power—0.15 picojoules/byte— as in the event that they have been one huge piece of silicon.
The staff examined the chip on a machine studying activity vital for augmented actuality, hand monitoring. The 3D chip was in a position to monitor two palms concurrently utilizing 40 % much less power than a single-die may do with just one hand. What’s extra, it did so 40 % sooner.
Along with machine studying, the chip can do picture processing duties. 3D made an enormous distinction right here, once more. Whereas the 2D model was restricted to compressed photos, the 3D chip can do full HD utilizing the identical quantity of power.
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